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[Idea] Verilog HDL - Designing a CPU...

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You might think that designing CPUs involves literally drawing out each transistor by hand. This, as it turns out, has not been the case for several decades. Rather, something called HDL (hardware description language) does this instead. For the designer, they merely design the chip at (roughly) the gate level, creating modules that perform functionality that can be re-used and tied together to form a CPU. This is harder than assembly language, but far easier than designing it by hand. 

In other words, there is literally a language that people use to design circuits. We haven't needed to do these by hand in a long, long time. 

Last year, I used something called Nand2Tetris (an educational tool designed to teach CPU fundamentals) to "design" (read: followed the instructions) a CPU from scratch. It was incredibly educational in a lot of ways. The tool has its own form of HDL that allows you to design an extremely simple 16 bit CPU from the ground up, literally gate-by-gate. The instructions are simple enough that someone with no experience could easily complete it within about two days or so. 

Now, I'm taking on the next challenge, and giving myself a year to do it. I'm going to redesign the same CPU in 8-bit form using real, industry standard languages: Verilog. This is what Intel and AMD and all of the other large companies use. 


Ideally, I would like to use 7400 series ICs (mostly adders, chips with NAND gates, and flip flop circuits) to actually implement the design on a real circuit board. This is probably biting off more than I can chew, so at the time, I'm just going to design it in software. This could be either very simple, or I could get carried away with it. Either way, it will be good experience, and I'll be posting progress here as I make new additions to the design. 

Has anyone attempted this before? If so, did you manage to translate the HDL implementation to a real hardware implementation?

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Verilog HDL - Designing a CPU... - by Darth-Apple - January 11th, 2020 at 11:03 PM

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